Creating and Accessing the Single Source of Truth with Agnisys Collaboration Framework

 



Recently, I wrote the blog post “Design, Verification, and Software Development Decisions Require a Single Source of Truth” and published it on our site. I pointed out how this 60-year-old term is highly relevant for our specification automation solutions for IP and system-on-chip (SoC) development. In today’s post, I’m exploring some of the issues that arise when you use a single source of truth (SSOT) on your project and show how you can make it easier with Agnisys Collaboration Framework.

An SSOT Refresher

In case it’s been a while since you read my previous post, let me remind you that SSOT is based on an information architecture in which all data is edited in a single master location. There may be local copies for better performance, but all writes propagate to the master. In our world, SSOT refers to the master source for your IP or chip specifications. All the design, verification, software, validation, and documentation files that we automatically generate use this single, golden source.

The SSOT concept has several advantages. Since no teams maintain their own, independent specifications, there are no inconsistencies. Since all generated files come from the same versions of the specifications, there’s no divergence. When any changes are made to the specifications, the files are simply regenerated at the push of a button. All teams remain synchronized and aligned throughout the entire project.

Practical Challenges

Teams who see the value in SSOT can implement it easily, but making sure that it works seamlessly and flawlessly is not so simple. Since engineers often save local copies of files in the course of editing them, there needs to be some notion of check-in and revision control in place. When changed specifications are ready for project-wide consumption, only then are they used to update the SSOT and trigger the re-generation of project files.

The teams accessing the SSOT are diverse, often using different tools and platforms. Access from multiple types of computers might be needed. Further, the teams are very likely to be geographically dispersed. Global collaboration implies a global workspace and revision control, plus excellent security to protect confidential data. Fast access to the SSOT for both downloads and updates must be provided despite the physical distance.

Introducing Collation Framework

In my previous post, I introduced SSOT while “not worrying about the messy details of local copies, how updates are made, and so forth.” We didn’t want to leave it up to our users to figure all this out. Our Collaboration Framework (CF) is designed to address the challenges I’ve listed above and to make it much easier for you to implement a robust SSOT development process. It is designed to enable more efficient teams collaborating on IP and chip design, especially on the hardware-software interface (HSI).

Key features of CF include:

  • System for managing the SSOT
  • Centralized project management with real-time collaboration
  • Global collaboration with version control
  • Data security and confidentiality with access control
  • Visual Studio Code (VS Code) integration with powerful PSS and System RDL editor extensions
  • Advanced and scalable programmers reference manual view
  • Flexible deployment options (intranet or cloud based)
  • Leverage of Agnisys IDesignSpec™ Suite   of specification automation tools

Support for Global Teams

CF supports team collaboration with real-time editing capabilities, enabling multiple users to work on a project simultaneously. This ensures streamlined workflows, reduces redundancy, and significantly enhances efficiency across hardware and software teams. We use a centralized Git-based workspace to facilitate global collaboration. Customizable admin rights enable selective team and project access to ensure data security and confidentiality.

CF helps you create and maintain a centralized SSOT for specification of hardware and software design. This leads to reduced bug count, a more efficient design process, and faster convergence to tapeout for shorter time to market (TTM). Specifications can be edited using the popular VS Code integrated development environment (IDE) platform. The PSS and SystemRDL editors have syntax highlighting, auto-completion, real-time error detection, linting, and more, for highly effective coding.

Choose Your Own Format

For the broadest possible industry deployment, CF supports a wide range of input and output file formats. Text-based input formats include SystemRDL, PSS, IP-XACT, and JSON. Outputs include:

  • Register transfer level (RTL) designs
  • Universal Verification Methodology (UVM) models, testbenches, and tests
  • C/C++ headers and tests
  • User-quality documentation.

You can generate dynamic and interactive programmer’s reference manuals with advanced search, sort, and custom filtering capabilities. This makes it easy for all hardware, software, firmware, verification, validation, and bringup teams to use shared documentation in ways most suitable for their own needs. Even for large HTML files, CF responds quickly, with smooth scrolling that eliminates pagination delays. Documentation can be easily shared via links with dynamic real-time updates.

CF-Image
Figure 1
CF-image
Figure 2

Conclusion

SSOT has proven to be a solid foundation for IP and SoC development, and we can help you succeed from your very first project. Our IDesignSpec Suite is based entirely on golden specifications, and CF ensures that such specifications can be used on large, geographically diverse teams. You can deploy from Linux, Windows, and macOS platforms to ensure that all team members are covered. You have complete security controls to ensure that no one steals your innovative designs.

You can develop your designs faster, with fewer bugs, and with less overhead. Adopting SSOT and Agnisys is one of the easiest and best decisions you’ll ever make.

 

Comments

Post a Comment

Popular posts from this blog

Deep Dive into UVM Register Model | Agnisys Technology

Image
  UVM Register Model, a key component of the Universal Verification Methodology (UVM), is a standardized methodology for verifying digital designs. It provides a framework for creating robust and reusable testbenches in the field of hardware verification. One essential aspect of UVM is its Register Abstraction Layer (RAL), which enables efficient verification of register-rich designs. In this article, we'll take a closer look at the UVM Register Model and explore its key components and concepts. Register Abstraction Layer (RAL) The  UMV Register Layer  is designed to model and verify register-based functionalities in a design. This includes registers, memory-mapped registers, and the associated fields within those registers. The primary purpose of RAL is to provide a systematic and efficient way of accessing and manipulating registers during verification. RAL Model in UVM Environment The UVM environment is a collection of components, including the genera...
Read more

Generate an Interactive Graphical View to Better Visualize Your Register Map

Image
  Managing and visualizing register maps is critical for any chip design team. Complex IPs and SoCs demand tools that offer not just detailed documentation but also dynamic, interactive, and customizable outputs to streamline collaboration across design, verification, firmware, software, and validation teams.  IDesignSpec , a solution that transforms static register data into dynamic collateral files, is capable of generating interactive HTML outputs for advanced visualization and efficient management. Next-Level Documentation: Interactive HTML Output IDesignSpec’s  collaboration framework   redefines register map visualization by generating  dynamic HTML outputs  with advanced navigation features. This output isn’t just documentation—it’s a fully interactive experience designed to enhance user productivity: Smart Search Features Quickly locate components by their name or address Perform advanced regex-based searches for precise data retrieval Sorting and C...
Read more

How Agnisys is Revolutionizing Chip Design with AI and AI-Enabled Chips

Image
  In the ever-evolving semiconductor landscape, the integration of Artificial Intelligence (AI) in chip design and the creation of AI-specific chips have emerged as transformative forces. The complexity of modern System-on-Chip (SoC) designs, coupled with the growing demand for AI-powered solutions, has fueled the need for innovative approaches to hardware design and development. At Agnisys, we are pioneering these advancements by leveraging AI to optimize the design process while crafting cutting-edge AI chips that redefine performance and efficiency. AI-Driven SoC Design: Bridging Complexity with Innovation The design and verification of a SoC involve managing an intricate web of components, specifications, and workflows. From designing Control and Status Registers (CSRs) and memory maps to integrating third-party IPs, each step requires precision and collaboration. AI enhances this process by introducing intelligent automation, pattern recognition, and predictive analysis, enabl...
Read more