DAC 2024 at Agnisys

At DAC 2024, Agnisys will be at the forefront of numerous activities, including our engaging Exhibitor Forum presentation, an exciting design contest featuring our IDS-NG tool, and our sponsorship of 'I LOVE DAC.' Join us to explore live demos, interactive sessions, and hands-on experiences that highlight our innovations in design automation. 



I LOVE DAC PROMOTION

We are sponsoring 'I LOVE DAC' at this year's DAC event! We're thrilled to share 44 promo codes for access to premium Engineering Tracks at this year's DAC event which includes Keynotes, SKYTalks & TechTalks, Engineering Track Presentations, Engineering Track Posters, DAC Pavilion and Exhibitor Forum, Exhibits, Tuesday Career Development Day, Hands-On Training, DAC Networking Events. Take advantage of this limited-time offer and secure your spot at the forefront of engineering innovation. Fill the form on the right and on a first-come-first serve basis you may be able to get one of the codes.

AGNISYS DESIGN CONTEST 

At the Agnisys Booth, you will discover how easy it is to use IDS-NG for creating digital designs. As the fastest way to get to market, IDS-NG eliminates the need for manual verification, validation, and integration. Attend a short demo to see IDS-NG in action, then participate in our exciting design contest. In this contest, participants will use IDS-NG to create their own digital designs, putting their skills to the test in a fun and competitive environment. This is a fantastic opportunity to learn a revolutionary way to design hardware, gain hands-on experience with IDS-NG, and compete for recognition and rewards.

Create a Design and see it work in no time without the need for verification, validation and debug - that's the power of IDesignSpec-NG.

  • Win Attractive Prices. 

  • Collect your participation gift.

  • Come back at 5:00 PM for the raffle.

EXHIBITOR FORUM

At the exhibitor forum we'll be presenting on the topic of “Object-Oriented Embedded Hardware for Operational Excellence”, Object-oriented software has made its mark in the industry. It has helped create large software systems. Coming from Software-industry it has been adopted by hardware verification in the form of languages like SystemVerilog and SystemC and methodologies like UVM. But what about embedded hardware?
This presentation will discuss how embedded hardware can be presented in an object-oriented way to firmware and lower levels of system software. We will review the industry standards and non-standard formats that are currently prevalent in this space.

Date: Wednesday 26, 2024

Time: 11:15AM - 11:45AM PDT

Location: Exhibitor Forum, Level 1 Exhibit Hall

Duration: 30 mins

Comments

Post a Comment

Popular posts from this blog

Deep Dive into UVM Register Model | Agnisys Technology

Image
  UVM Register Model, a key component of the Universal Verification Methodology (UVM), is a standardized methodology for verifying digital designs. It provides a framework for creating robust and reusable testbenches in the field of hardware verification. One essential aspect of UVM is its Register Abstraction Layer (RAL), which enables efficient verification of register-rich designs. In this article, we'll take a closer look at the UVM Register Model and explore its key components and concepts. Register Abstraction Layer (RAL) The  UMV Register Layer  is designed to model and verify register-based functionalities in a design. This includes registers, memory-mapped registers, and the associated fields within those registers. The primary purpose of RAL is to provide a systematic and efficient way of accessing and manipulating registers during verification. RAL Model in UVM Environment The UVM environment is a collection of components, including the genera...
Read more

Generate an Interactive Graphical View to Better Visualize Your Register Map

Image
  Managing and visualizing register maps is critical for any chip design team. Complex IPs and SoCs demand tools that offer not just detailed documentation but also dynamic, interactive, and customizable outputs to streamline collaboration across design, verification, firmware, software, and validation teams.  IDesignSpec , a solution that transforms static register data into dynamic collateral files, is capable of generating interactive HTML outputs for advanced visualization and efficient management. Next-Level Documentation: Interactive HTML Output IDesignSpec’s  collaboration framework   redefines register map visualization by generating  dynamic HTML outputs  with advanced navigation features. This output isn’t just documentation—it’s a fully interactive experience designed to enhance user productivity: Smart Search Features Quickly locate components by their name or address Perform advanced regex-based searches for precise data retrieval Sorting and C...
Read more

How Agnisys is Revolutionizing Chip Design with AI and AI-Enabled Chips

Image
  In the ever-evolving semiconductor landscape, the integration of Artificial Intelligence (AI) in chip design and the creation of AI-specific chips have emerged as transformative forces. The complexity of modern System-on-Chip (SoC) designs, coupled with the growing demand for AI-powered solutions, has fueled the need for innovative approaches to hardware design and development. At Agnisys, we are pioneering these advancements by leveraging AI to optimize the design process while crafting cutting-edge AI chips that redefine performance and efficiency. AI-Driven SoC Design: Bridging Complexity with Innovation The design and verification of a SoC involve managing an intricate web of components, specifications, and workflows. From designing Control and Status Registers (CSRs) and memory maps to integrating third-party IPs, each step requires precision and collaboration. AI enhances this process by introducing intelligent automation, pattern recognition, and predictive analysis, enabl...
Read more