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Showing posts from July, 2025

The Future of Chip Design: Key Trends, Challenges and Innovations in Semiconductors

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  Semiconductor development is one of the most dynamic industries in history. Change is constant, stemming from evolution in underlying technologies and architecture, punctuated by the occasional revolution, such as the recent focus on AI. For this post, I’m focusing on five key aspects of change in chip design that we are seeing widely in our user base. If you’re facing challenges related to these trends, I’ll let you know how we can help. AI Is Everywhere You can’t pick up a newspaper (literally or digitally) these days without seeing AI in the headlines. The rapid increase in capabilities and the potential for the future are astounding. Even if your only interaction with AI is getting more focused search results, you can appreciate how much has changed so quickly. As engineers, we understand more about the hardware and software technology that makes the capabilities of AI possible, and these are impressive as well. With AI affecting almost every aspect of our lives, it is not su...

Accelerating FPGA Development: From Specification to System Validation with IDS-FPGA

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  Join Agnisys for a technical deep dive into IDS-FPGA, a comprehensive solution that automates the end-to-end FPGA development process, from high-level design specification through RTL generation, system integration, simulation, and hardware/software co-verification. This webinar features a complete design flow demonstration using a real-world Ethernet Generator and Monitor example, illustrating how IDS-FPGA helps eliminate manual steps, reduce errors, and improve design quality and turnaround time. This flow is demonstrated using an Ethernet Generator and Monitor design example. 1. Design Specification using our GUI based tool The process begins with our GUI-based tool used to define hardware architecture at a high level. Designers can configure components such as interfaces, registers, memories, FIFOs, and connectivity. Our GUI based tool generates: Synthesizable RTL (Verilog/SystemVerilog) Addressable register maps Design documentation Interface metadata (AXI/APB/AHB, etc.) 2. ...