Agnisys

  Introduction In the field of hardware verification, the Universal Verification Methodology (UVM) is a powerful framework that provides a systematic and standardized method for digital design verification. At the heart of UVM-based verification is a critical component known as the Register Abstraction Layer (RAL). In this blog article, we will look at the  Register Model in UVM  and how it plays an important part in maintaining a robust and efficient verification process. What is a UVM register model? UVM RAL UVM RAL provides an organized and standardized approach to modelling and verifying register and memory mappings in a digital design. It is made up of a hierarchy of blocks represented by UVM class objects, which are structured similarly to registers and memory in design.   Figure 1. Building block for UVM RAL Register model refers to the configuration of the DUT register/memory/regfile/block in the UVM RAL module for testing purposes. UVM RAL provides the base ...

  Register automation is an integral part of   IP and SoC development . Long ago,  design, verification, firmware, and documentation teams preferred doing register management manually or each team wrote their own scripts for limited automation. Later, companies started doing this automation at the organization level. Central scripts were written for register automation for design, verification, firmware, and documentation teams, but still each had their own specifications. This led to many iterations between these teams before different collaterals were all brought in sync. As design complexity grew, maintaining these scripts became difficult, and commercial EDA tools took their place. Simultaneously, many open source tools also cropped up that could be used for register automation. Although commercial tools have their own value proposition, open source tools also have their use cases. The five primary reasons why you might use open source tool are: 1. Cost Open sour...