Agnisys

  Chip designers  have always reused circuitry, when possible, to shrink the project schedule, save resources, and reduce risk by using a silicon-verified design. Many types of  chip design  elements are common in diverse applications, and gradually these became packaged into libraries shared across all the teams in a company. The advent of register-transfer-level (RTL) descriptions made reuse much easier since logic synthesis tools could map the same code to many different silicon technologies. Rise of Reusing IP Chips In the 1990s, internal reuse was complemented by a robust commercial silicon intellectual property (IP) industry, in which both digital RTL cores and hard macros for analog elements were licensed to many different customers. Chip designers could focus their time and effort on differentiating features rather than common functions where custom  chip design  yielded no competitive advantage. Today’s large system-on-chip (SoC) designs contain hu...

  Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging. Even a small error in the hardware design can require a very expensive chip turn to fix. Of course, this also delays time to market (TTM), as do any unexpected issues arising in design verification, hardware/software co-verification (also known as pre-silicon validation), and post-silicon validation in the bringup lab. Some of this is hard to avoid, due to the sheer size and complexity of today’s designs. However, there are three problems that commonly arise in the design, verification, and validation flow that can be avoided by rigorous application of specification automation. The Imprecision of Natural Language Every design, whether a single IP block or a room-sized massively parallel supercomputer, starts with a specification. The product marketing/management team defines the target market, talks to leading-edge customers, surveys the competition, ...

  As chips get ever larger and more complex, one thing is for certain: the electronic design automation (EDA) tools, techniques, and methodologies used to develop silicon become more sophisticated. Every stage of chip development—architecture, design, implementation, verification, programming, validation, and test—consumes more time and resources. Continual improvement in EDA is the only way to avoid total project meltdown. This situation puts enormous pressure on Agnisys and other solutions providers to adopt the latest and greatest technologies to help our users succeed.  It's easy to check off a list of development improvements that have helped over the years: automated layout, register transfer level (RTL) design, logic synthesis, constrained-random testbenches, formal and static verification, automated test pattern generation (ATPG), and more. It seems that every few years a new technique, guided by a comprehensive methodology, emerges to tackle the ever-rising size and c...